The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2000

Filed:

Feb. 10, 1997
Applicant:
Inventors:

Bomy Able Chen, Hopewell Junction, NY (US);

Subhash Balakrishna Kulkarni, Peekskill, NY (US);

Jerome Brett Lasky, Essex Junction, VT (US);

Randy William Mann, Jericho, VT (US);

Edward Joseph Nowak, Essex Junction, VT (US);

Werner Alois Rausch, Stormville, NY (US);

Francis Roger White, Essex Junction, VT (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438152 ; 438149 ; 438783 ;
Abstract

An improved field effect transistor (FET) structure is disclosed. It comprises a first insulator layer containing at least one primary level stud extending through the layer; an undoped cap oxide layer disposed over the insulator layer and abutting the upper region of each stud; a primary level thin film transistor (TFT) disposed over the undoped cap oxide layer; and a planarized oxide layer disposed over the TFT. Multiple TFT's can be stacked vertically, and connected to other levels of studs and metal interconnection layers. Another embodiment of the invention includes the use of a protective interfacial cap over the surface of tungsten-type studs. The FET structure can serve as a component of a static random access memory (SRAM) cell. Related processes are also disclosed.


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