The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2000

Filed:

Sep. 26, 1997
Applicant:
Inventors:

Takeshi Miyajima, Kariya, JP;

Norihito Tokura, Okazaki, JP;

Kazukuni Hara, Obu, JP;

Hiroo Fuma, Gifu, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257 76 ; 257 77 ; 257329 ; 257330 ; 257332 ; 257333 ; 257334 ; 257289 ;
Abstract

A silicon carbide semiconductor device having a high blocking voltage, low loss, and a low threshold voltage is provided. An n.sup.+ type silicon carbide semiconductor substrate 1, an n.sup.- type silicon carbide semiconductor substrate 2, and a p type silicon carbide semiconductor layer 3 are successively laminated on top of one another. An n.sup.+ type source region 6 is formed in a predetermined region of the surface in the p type silicon carbide semiconductor layer 3, and a trench 9 is formed so as to extend through the n.sup.+ type source region 6 and the p type silicon carbide semiconductor layer 3 into the n.sup.- type silicon carbide semiconductor layer 2. A thin-film semiconductor layer (n type or p type) 11a is extendedly provided on the surface of the n.sup.+ type source region 6, the p type silicon carbide semiconductor layer 3, and the n.sup.- type silicon carbide semiconductor layer 2 in the side face of the trench 9. A gate electrode layer 13 is disposed through a gate insulating layer 12 within the trench 9. A source electrode layer 15 is provided on the surface of the p type silicon carbide semiconductor layer 3 and on the surface of the n.sup.+ type source region 6, and a drain electrode layer 16 is provided on the surface of the n.sup.+ type silicon carbide semiconductor substrate 1.


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