The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 18, 2000
Filed:
Oct. 29, 1997
Mark I Gardner, Cedar Creek, TX (US);
H Jim Fulford, Austin, TX (US);
Dim-Lee Kwong, Austin, TX (US);
Advanced Micro Devices, Sunnyvale, CA (US);
Abstract
A process for fabricating a gate dielectric stack of a MOS transistor. A native oxide film is formed on an upper surface of a semiconductor substrate. A silicon nitride layer is then deposited on the native oxide film. A final dielectric film is then formed on the silicon nitride film. A dielectric constant of the final dielectric film is in the range of approximately 20-200. The substrate is then annealed in an inert ambient to produce the gate dielectric stack. An equivalent silicon dioxide thickness of the dielectric stack is typically in the range of approximately 5-20 angstroms whereby a gate dielectric stack suitable for use in deep sub-micron transistor is fabricated with a film thickness substantially in excess of an electrically equivalent silicon dioxide film. A suitable material for the final dielectric film includes oxides comprising oxygen and an element such as beryllium, magnesium, calcium, zirconium, titanium, or tantalum.