The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2000

Filed:

May. 12, 1997
Applicant:
Inventors:

Toshihiko Yasue, Gifu, JP;

Yasuji Hiramatsu, Gifu, JP;

Hideki Yano, Gifu, JP;

Yoshifumi Ishitani, Gifu, JP;

Yoichiro Kawamura, Gifu, JP;

Hideki Murase, Gifu, JP;

Ayumi Suzuki, Gifu, JP;

Masato Kawade, Gifu, JP;

Motoo Asai, Gifu, JP;

Assignee:

Ibiden Co., Ltd., Gifu, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B32B / ;
U.S. Cl.
CPC ...
428209 ; 174255 ; 174258 ; 428901 ;
Abstract

It is to provide a multilayer printed circuit board having excellent resolution, interlaminar insulation property and resistance to cool-heat shock without forming unevenness on the surface and lowering peel strength even if the thickness of the resin insulating layer is thin. The invention proposes a multilayer printed circuit board comprising an upper conductor circuit layer, a lower conductor circuit layer and a resin insulating layer electrically insulating both the conductor circuit layers, in which the resin insulating layer is a composite layer comprised of an layer made from a heat-resistant resin hardly soluble in acid or oxidizing agent as a lower layer and an adhesive layer for electroless plating made from a heat-resistant resin as an upper layer, and if necessary, a resin is filled in a concave portion created between conductor insulating circuits of the lower layer so as to render the surface into the same plane as the surface of the conductor circuit.


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