The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 23, 1999
Filed:
May. 27, 1997
John T MacKay, San Jose, CA (US);
Thomas E Molinaro, Newark, CA (US);
David G Love, Pleasanton, CA (US);
Patricia R Boucher, Fremont, CA (US);
Fujitsu Limited, , JP;
Semi-Pac, Sunnyvale, CA (US);
Abstract
Methods for forming solder bumps on integrated circuit chips (and other similar circuitized units). A screening stencil is laid over the surface of the substrate and solder paste material is deposited into the stencil's apertures with a screening blade. The stencil is placed in such a manner that each of its apertures is positioned over a substrate pad, upon which a solder bump is to be formed. Next, a flat pressure plate is laid over the exposed top surface of the stencil, which creates a fully enclosed or 'captured', cell of solder paste within each stencil aperture. Then, with the stencil and plate remaining in place on top of the substrate, the substrate is heated to a temperature sufficient to reflow the solder paste material. After reflow, the substrate is cooled, and the pressure plate and stencil are thereafter removed, leaving solder bumps on the substrate. The use of the pressure plate ensures the proper formation of the solder bumps at high densities of solder bumps (i.e., high densities corresponding to small solder bump sizes and small pitch distances between solder bumps).