Uv methods for screening open circuit defects in cmos integrated circuits

Abstract

A method for detecting defects in a CMOS integrated circuit. In one embodiment, all pins on an integrated circuit chip are initially grounded. Next, the chip is exposed to ultraviolet light which will discharge the voltage on a floating gate in the integrated circuit to zero volts. Next, the chip is powered up to a normal operating condition voltage levels. That is, normal operating voltages are applied to V.sub.CC while V.sub.SS pins remain grounded. As a result, the floating gates in the integrated circuit will stabilize at an intermediate logic value determined by the voltage divider relationship determined by the parasitic capacitances between the floating gates, V.sub.CC and V.sub.SS. Next, IDDQ testing is performed on the chip. Since the floating gates have been set to an intermediate logical value, any floating gate defects will be detected with IDDQ testing since a substantially high quiescent current will result with the floating gate node voltages set to an intermediate value. Thus, in accordance with the teachings of the present invention, devices suffering from open circuit floating gate may be identified.