The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 1999
Filed:
Jun. 11, 1997
Richard G Cliff, Milpitas, CA (US);
Francis B Heile, Santa Clara, CA (US);
Joseph Huang, San Jose, CA (US);
Fung Fung Lee, Milpitas, CA (US);
Cameron McClintock, Mountian View, CA (US);
David W Mendel, Sunnyvale, CA (US);
Bruce B Pedersen, San Jose, CA (US);
Srinivas T Reddy, Fremont, CA (US);
Chiakang Sung, Milpitas, CA (US);
Kerry Veenstra, San Jose, CA (US);
Bonnie I Wang, Cupertino, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A programmable logic device has regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Horizontal interconnection conductors are associated with each row, and vertical interconnection conductors are associated with each column. Local conductors are interspersed between adjacent pairs of regions in each row for supplying signals to the regions on both sides of the local conductors. Subregions of programmable logic in each region generally have a local output and a global output. The global output is only usable to output to the relatively long-distance horizontal and vertical conductors. The local output is additionally usable as a local feedback and as a local connection to an adjacent region.