The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 1999
Filed:
Dec. 29, 1997
Ching-Yuan Ho, Hsinchu, TW;
Shang-Yun Hou, Hsinchu, TW;
Worldwide Semiconductor Manufacturing Corp., Hsinchu, TW;
Abstract
A method for forming interconnection plugs comprising the steps of providing a substrate, then forming a dielectric layer having an opening that exposes a pad area for connection with other structures. Next, a glue layer is formed lining the opening and the dielectric layer. Subsequently, plug material is deposited into the opening to form a plug layer. This is followed by etching back the plug layer to a level higher than the glue layer that formed on the top of the dielectric layer. Thereafter, a metallic layer is formed over the plug layer, and a photoresist layer is then coated over the metallic layer. The metallic layer and the plug layer are then patterned by etching such that the plug layer is turned a plug. The characteristic of this invention lies in retaining a portion of the plug layer after the first etching such that the etched plug layer is at a level higher than the glue layer. Through combining the patterning of the metallic layer and the plug layer, one etching step is saved, moreover, recess formation can be prevented, thereby leading to no deterioration of electrical properties or lowering of the yield in the semiconductor devices.