The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 1999
Filed:
Apr. 26, 1999
Tsung-Yuan Hung, Tainan, TW;
United Semiconductor Corp., Hsinchu, TW;
United Microelectronics Corp., Hsinchu, TW;
Abstract
A method of manufacturing a CMOS. A substrate is provided, wherein the substrate has a first conductive-type well, a second conductive-type well, an isolation structure formed therein, a first gate electrode on the second conductive-type well and a second gate electrode on the first conductive-type well. The first conductive-type well and the second conductive-type well are partly isolated from each other by the isolation structure. A first offset spacer is formed on a sidewall of the first and the second gate electrodes and a second offset spacer on a sidewall of the first offset spacer, wherein a portion of the first offset spacer extends on a surface of the substrate and the second offset spacer is on the portion of the first offset spacer. A first LDD region having the first conductive type is formed in a portion of the second conductive-type well exposed by the first gate electrode, the first offset spacer and the second offset spacer. The second offset spacer is removed to expose a portion of the first offset spacer extending on a portion of a surface of the substrate. A second LDD region having the second conductive type is formed in a portion of the first conductive-type well and exposed by the second gate electrode and the first offset spacer under the portion of the first offset spacer extending on a portion of a surface of the substrate. A spacer is formed on a sidewall of the first and the second gate electrodes. A first doped region having the first conductive type is formed in a portion of the second conductive-type well exposed by the first gate electrode, the first offset spacer and the spacer. A second doped region having the second conductive type is formed in a portion of the first conductive-type well exposed by the second gate electrode, the first offset spacer and the spacer.