The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 1999
Filed:
Nov. 12, 1997
Chun Hsiung Hung, Hsinchu, TW;
Tzeng-Huei Shiau, Hsin-pu, TW;
Yao-Wu Cheng, Taipei, TW;
I-Long Lee, I-Lan, TW;
Fuchia Shone, Hsinchu, TW;
Ray-Lin Wan, Fremont, CA (US);
Macronix International Co., Ltd., Hsinchu, TW;
Abstract
A new flash memory cell structure and operational bias is based on the use of a triple well flash memory cell which allows pre-programming by Fowler Nordheim (F-N) tunneling over blocks of cells at a time. The floating gate memory cell is made in a semiconductor substrate having a first conductivity type, such as p-type. A first well within the substrate by having a second conductivity type different than the first conductivity type is included. A second well within the first well is also included having the first conductivity type. A drain and a source are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain and the source. A floating gate and control gate structure is included over the channel area. The floating gate memory cell is coupled with circuits that induce F-N tunneling of electrons out of the floating gate into the channel area of the substrate for erasing by applying a positive voltage to the second well, such as a voltage higher than the supply voltage, applying a positive voltage to the first well, which is substantially equal to the positive voltage of the second well, applying a negative voltage to the control gate of the cell, while the substrate is grounded. A block wide pre-program operation involves F-N tunneling of electrons into the floating gate from the channel area, using a negative voltage in the second well.