The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 1999

Filed:

Jun. 18, 1997
Applicant:
Inventor:

Brian J Arkin, Pleasanton, CA (US);

Assignee:

Credence Systems Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
327276 ; 327284 ; 327277 ;
Abstract

A programmable delay circuit produces an OUTPUT signal following an INPUT signal with a delay selected by input delay selection data. The delay circuit includes a tapped delay line, a multiplexer, a delay adjustment stage and a programmable encoder. The delay line includes a set of N delay elements connected in series for successively delaying the INPUT signal to produce a set of N output TAP signals. The multiplexer passes a selected TAP signal to the delay adjustment stage. The delay adjustment stage delays the selected TAP signal to produce the OUTPUT signal. The programmable encoder encodes the input delay selection data to provide signals for controlling the multiplexer and for adjusting the delay of the delay adjustment stage. The manner in which the encoder encodes each separate delay selection data value is adjustable so that each of the N selectable delays can be separately calibrated.


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