Power mosfet fabrication process to achieve enhanced ruggedness, cost

Abstract

This invention shows an improved method for fabricating a MOSFET transistor on a substrate to improve a device ruggedness. The method includes the steps of: (a) forming an epi-layer of a first conductivity type as a drain region on the substrate and then growing an initial oxide layer over the epi-layer; (b) applying an active mask for etching the initial oxide layer to define an active area and forming a gate oxide layer thereon followed by depositing an overlaying polysilicon layer; (c) applying a poly mask for etching the polysilicon layer to define a plurality of poly gates; (d) removing the poly mask and then carrying out a body implant of a second conductivity type followed by performing a body diffusion for forming a plurality of body regions and for growing a thin oxide layer overlaying the ploy gates and silicon surface; (e) depositing a blocking-and-alignment layer of dielectric material with a pre-designated thickness followed by implanting body-dopants of the second conductivity type at an energy level correlating to the thickness of the blocking-and-alignment layer to form a buried body-dopant region at a pre-determined depth in each of the body regions (f) removing the blocking-and-alignment layer followed by applying a source blocking mask for implanting a plurality of source regions in the body regions with ions of the first conductivity type followed by removing the source blocking mask; and (g) forming an insulation layer and applying a high temperature process for densification of the insulation layer and further for actuating a diffusion of the source regions and the deep heavily-doped body-dopant regions. The deep heavily-doped body-dopant regions are formed immediately below the source regions whereby the device ruggedness is improved.