The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 1999

Filed:

Oct. 24, 1997
Applicant:
Inventors:

Shou-Yi Shiu, Hsin-Chu, TW;

Yu-Ping Fang, Miaoli, TW;

Hon-Hung Lui, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438 48 ; 438 54 ; 438 55 ; 438612 ; 438928 ; 136200 ; 136201 ; 136203 ; 136204 ; 136225 ; 136228 ; 136293 ; 361718 ;
Abstract

The present invention provides a structure and a method of fabricating a thermoelectric Cooler directly on the backside of a semiconductor substrate. The thermoelectric (TE) cooler (thermoelectric cooler) disperses heat from an integrated circuit (IC) that is formed on the front-side of the silicon substrate. Spaced first bonding pad holes 28 are formed in the backside of a substrate that expose bonding pads 24. Second holes 32 are formed between the spaced first bonding pad holes 28. A first insulating layer 34 is formed over the backside of the substrate, but not over the bonding pad 24. A metal layer is formed lining the first bonding pad holes 28. A polysilicon layer 46 is formed over the surface of the backside of the substrate in the second holes. The polysilicon layer is implanted thereby forming alternating adjacent N and P doped sections 46p 46n in the second holes. The adjacent N and P doped polysilicon sections 46n 46p are electrically connected to the bonding pads 24 by the metal layer 38.


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