The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 1999

Filed:

Oct. 31, 1997
Applicant:
Inventors:

Brian J Arkin, Pleasanton, CA (US);

David Scott, Fremont, CA (US);

Ha Nguyen, San Jose, CA (US);

Assignee:

Credence Systems Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
714738 ; 714 32 ;
Abstract

An integrated circuit tester includes a host computer, a pattern generator and a set of tester circuits. The tester circuits perform test activities on an integrated circuit in response to sequences of test control data arriving via a set of data lines. The host computer may write parameter control data into the tester circuits via a bus telling the tester circuits how to adjust various parameters of test activities to be performed in response to a next arriving sequence of test control data. The host computer is also linked to the pattern generator via that same bus and writes pattern control data into the pattern generator via the bus. The pattern control data tells the pattern generator to generate alternating sequences of test control data and pattern control data. As it is generated, each test control data sequence is delivered to the tester circuits via the data lines to tell the tester circuits how to carry out a sequence of test activities. As each parameter control data sequence is generated, the parameter control data is written into the tester circuits via the bus to set the test parameters for a next sequence of test activities to be performed. Thus once programmed with pattern control data from the host, the pattern generator can cause the tester circuits to carry out a sequence of tests and to appropriately adjust their test parameters before each test without further assistance from the host computer.


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