The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 10, 1999
Filed:
Jun. 04, 1997
Applicant:
Inventors:
James W Conary, Aloha, OR (US);
John A Deetz, Beaverton, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
713322 ;
Abstract
A method and apparatus for reducing the power consumption of an integrated circuit when the core logic of the integrated circuit is in the quiescent or idle state. The method and apparatus includes a phase locked loop (PLL) circuit for generating an internal clock, wherein the frequency of the internal clock is at a predetermined multiple of the frequency of the global clock signal. When the integrated circuit is quiescent, the present invention provides circuitry which permits the internal clock to be slowed to a lower frequency or the internal clock to be frozen to reduce power consumption.