The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 03, 1999
Filed:
Sep. 30, 1997
Synopsys, Inc., Mountain View, CA (US);
Abstract
A method for testing for power supply network voltage drop violations in an integrated circuit through a computer simulation. First, the IC chip area is divided into a number of discrete regions. The simulation time is divided into a number of time segments. Next, the average aggregate currents corresponding to the transistors for each of the regions are calculated for each of the time segments. Only when a peak average current occurs for any one of the plurality of regions is the power supply network of the IC chip simulated for that time segment. Based on the voltage drops as determined by the power network simulation, violation conditions can be easily identified. Thus, the power network of the IC chip is simulated only when there is found to be high switching activity in some region of the chip. This is more efficient than performing power network voltage drop analyses all the time, even when switching activity throughout the chip is low and the likelihood of any voltage drop violations is very low.