The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 1999
Filed:
Apr. 14, 1997
John Edward Cronin, Milton, VT (US);
Wayne John Howell, Williston, VT (US);
Howard Leo Kalter, Colchester, VT (US);
Patricia Ellen Marmillion, Colchester, VT (US);
Anthony Palagonia, Underhill, VT (US);
Bernadette Ann Pierson, South Hero, VT (US);
Dennis Arthur Schmidt, South Burlington, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Integrated Circuit ('IC') chips are formed with precisely defined edges and sizing. At the wafer processing level, trenches are lithographically etched in the kerf regions to define the edges of the IC chips on the wafer. The trenches are filled with insulating material, and upper level wiring and metallization is completed for the IC chips on the wafer. Further trenches are defined down to the filled previously formed trenches. The wafer is thinned from its bottom up to the filled trenches, and the insulating material therein is removed to separate the individual IC chips from the wafer. The precision of IC chip edge definition facilitates forming the IC chips into stacks more easily because many stack level alignment processes become unnecessary.