Process for manufacturing a dual floating gate oxide flash memory cell

Abstract

An improved floating gate memory cell, having a dual thickness floating gate oxide, minimizes the band-to-band tunneling current and hot hole injection current suffered by the device, maximizes the Fowler-Nordheim tunneling current, allows lower operational voltages and provides a scalable structure. The process for manufacturing the dual thickness floating gate oxide structure comprises the steps of (1) forming a thicker insulator region over a channel region on the substrate, the thicker insulator having a source side and a drain side; (2) forming a thinner insulator on one or both of the source side and the drain side of the thicker insulator, and over a tunnel region in the substrate that is adjacent to the channel region; and (3) after forming the thinner insulator, distributing dopants in the source and the drain so that a concentration of dopants in the tunnel region beneath the thinner insulator is near or greater than a degenerately doped concentration. The step of distributing the dopants involves a process which does not damage the thinner insulator in the tunnel region. The floating gate is formed over the thicker insulator and the thinner insulator, and a control gate insulator and control gate are formed to complete the structure of the device. In this manner, a high-quality tunnel oxide is grown over the substrate while it is moderately doped. After growing a high quality tunnel oxide, the source and drain dopants are distributed into the device. In the tunnel region, where the floating gate oxide is thinner, the concentration of dopants in the substrate is quite high due to the source and drain dopants. This prevents band bending, at a level sufficient to induce band-to-band tunneling. In the channel region, where the concentration of dopants is more moderate, the thicker insulator prevents formation of an electric field sufficient to induce significant band-to-band tunneling.