The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 1999
Filed:
Sep. 19, 1997
Ming-Lun Chang, Hsinchu, TW;
Winbond Electronics Corp., , TW;
Abstract
A method of planarizing an inter-metal dielectric layer includes providing a semiconductor substrate having a component layer formed thereon; and forming a metallic layer over the component layer. Then, portions of the metallic layer are etched to form metal pads on the metallic layer surface. Next, the metallic layer is patterned and portions of the metallic layer are etched to form a plurality of metal lines and trenches between the metal lines. Subsequently, a first oxide layer is deposited over the metal lines and the trenches, and then a spin on glass layer is formed over the first oxide layer, filling up the trenches. Thereafter, portions of the spin on glass layer are etched back to expose the metal pad and form a residual spin on glass layer, and then a second oxide layer is formed over the metal pad, the residual spin on glass layer and the first oxide layer. Portions of the second oxide layer are etched to form an opening in the second oxide layer that corresponds to the metal pad location. The opening is subsequently used to form a via plug.