The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 1999

Filed:

Dec. 16, 1997
Applicant:
Inventors:

Frans Peter Lautzenhiser, Noblesville, IN (US);

John Karl Isenberg, Rossville, IN (US);

James Edward Walsh, W. Lafayette, IN (US);

Adam Wade Schubring, Kokomo, IN (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B05D / ;
U.S. Cl.
CPC ...
427 96 ; 427258 ; 427384 ; 427402 ;
Abstract

An improved method of manufacturing multi-layer thick film circuits that effectively eliminates the trade-off between thickness and definition, permitting dielectric layers of increased thickness with no pin-holes, and at the same time, more precise definition of dielectric features, such as via openings and solder stops. The dielectric features are precisely defined by an initial thin layer of dielectric material, referred to as a feature definition print, or FDP. After the FDP has been dried but not yet fired, a via can be formed by printing a comparatively thick cover layer of dielectric, over-lapping the edges of the FDP. Due to the porous nature of the dried but not fired FDP, it absorbs solvent from the dielectric cover layer, which inhibits the spreading of the dielectric cover layer. The FDP is then co-fired with the first dielectric layer, and a second dielectric layer may be provided atop the fired first layer to further increase the overall dielectric thickness, if so desired. This results in a thicker dielectric layer for the same number of successive printing steps, and at the same time, smaller dielectric features. The thicker dielectric layer provides improved isolation between circuit layers, and the smaller dielectric features increase the available surface area for conductors and components on the upper dielectric layer. Additionally, process robustness is improved, since there is less fine tuning and batch-to-batch variation when used in high volume production.


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