The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 1999

Filed:

Oct. 15, 1997
Applicant:
Inventors:

Masayuki Nakamura, Ome, JP;

Masatoshi Hasegawa, Ome, JP;

Seiji Narui, Hamura, JP;

Yousuke Tanaka, Ome, JP;

Shinichi Miyatake, Hamura, JP;

Shuichi Kubouchi, Fussa, JP;

Kazuhiko Kajigaya, Iruma, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365207 ; 365205 ;
Abstract

In a dynamic RAM having a memory cell array in which a dynamic memory cell is arranged at an intersection between a word line and one of a pair of bit lines, a select level signal corresponding to a supply voltage and an unselect level signal corresponding to a negative potential lower than circuit ground potential are supplied to the word line. A signal of a memory cell read to the pair of bit lines by a sense amplifier that operates on the circuit ground potential and an internal voltage formed by dropping the supply voltage by an amount equivalent to the threshold voltage of the address select MOSFET is amplified. The dynamic RAM has an oscillator that receives the supply voltage and circuit ground potential and a circuit that receives an oscillation pulse generated by the oscillator to generate the negative potential.


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