The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 11, 1999
Filed:
Sep. 26, 1997
Yi-Huang Wu, Tainan Hsien, TW;
Der-Chen Chen, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
An FET semiconductor substrate includes source/drain regions with an outer buried contact region overlapping the drain region, a gate oxide layer, and a polysilicon layer over the gate oxide layer. An inner buried contact opening through the polysilicon and the gate oxide layer reaches down to the substrate over the outer buried contact region. An inner buried contact region, within the outer buried contact region, is self-aligned with the buried contact opening. A second polysilicon layer formed over the gate oxide layer reaches down through the buried contact opening into contact with the inner buried contact region. An interconnect and a gate electrode are formed from the polysilicon layers. Source/drain regions are self-aligned with the gate electrode and whereas the drain region is spaced from the inner buried contact region, the outer buried contact region interconnects the drain region with the inner buried contact region.