The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 27, 1999

Filed:

Nov. 21, 1996
Applicant:
Inventors:

James M Apland, Gilroy, CA (US);

David D Eaton, San Jose, CA (US);

Andrew K Chan, Palo Alto, CA (US);

Assignee:

QuickLogic Corporation, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L / ;
U.S. Cl.
CPC ...
380-3 ; 380-4 ; 326 41 ;
Abstract

A field programmable gate array has a security antifuse which when programmed prevents readout of data indicative of how the interconnect structure is programmed but which does not prevent readout of data indicative of which other antifuses are programmed. In some embodiments, the programming control shift registers adjacent the left and right sides are the field programmable gate array are disabled when the security antifuse is programmed but the programming control shift registers adjacent the top and bottom sides of the field programmable gate array are not disabled. A second security antifuse is also provided which when programmed disables a JTAG boundary scan register but does not disable a JTAG bypass register. Information can therefore be shifted through the JTAG test circuitry without allowing the JTAG circuitry to be used to extract information indicative of how the interconnect structure is programmed. Logic module and interface cell scan paths are provided and special test instructions are supported which allow test vectors to be loaded into the logic module and interface cell scan paths.


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