The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 1999
Filed:
Dec. 08, 1997
Fwu-Iuan Hshieh, Saratoga, CA (US);
Magepower Semiconductor Corporation, San Jose, CA (US);
Abstract
This invention discloses a DMOS planar power device having a plurality of transistor cells formed in a semiconductor substrate with a drain region of a first conductivity type disposed at a bottom surface of the substrate. Each of the DMOS transistor cells includes a polysilicon segment constituting a gate supported on a top surface of the substrate wherein the gate being disposed substantially in a center portion of the transistor cell. The DMOS transistor cell further includes a source region of the first conductivity type disposed in the substrate surrounding edges of the gate with a portion extends underneath the gate. The DMOS transistor cell further includes a body region doped with a body dopant of a second conductivity type disposed in the substrate encompassing the source region. The body region has a portion extending underneath the gate having a under-the-gate distance less than a lateral diffusion of the body dopant and the body region having outer edges extending outwardly to neighboring transistor cells. The DMOS transistor cell further includes a shallow low-concentration first-conductivity-type region under the gate wherein the shallow low-concentration first-conductivity-type region having a depth shallower than a depth of the source region.