The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 06, 1999
Filed:
Apr. 17, 1997
Tadayasu Miki, Yamanashi, JP;
Shigeo Ogasawara, Higashimurayama, JP;
Noriaki Oka, Kodaira, JP;
Shigeru Takahashi, Tachikawa, JP;
Mitsuaki Katagiri, Higashimurayama, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A semiconductor integrated circuit having three or more layers of wiring is provided with a plurality of lines of bonding pads arranged along the outer peripheral portion of a semiconductor chip. The bonding pads on the inner line side and those on the outer line side are arranged in a zigzag manner. First outgoing wiring for electrically connecting the bonding pads on the inner line side and internal circuits (input/output buffer circuits) is formed in one layer of wiring or a plurality of layers of wiring including at least the uppermost layer of wiring, and second outgoing wiring for electrically connecting the bonding pads on the outer line side and the internal circuits (the input/output buffer circuits) is formed in a plurality of layers of wiring other than the layer in which the first outgoing wiring is formed. Further, the first outgoing wiring and the second outgoing wiring are formed in different layers of wiring and at least one of the outgoing wiring films is formed of a plurality of layers of wiring.