The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 06, 1999
Filed:
Jun. 03, 1996
Chau-Neng Wu, Kaoshiung Hsien, TW;
Ming-Dou Ker, Tainan Hsien, TW;
Winbond Electronics Corp., Hsinchu, TW;
Abstract
A capacitor-triggered electrostatic discharge (ESD) protection circuit is disposed between a metal pad and V.sub.ss potential level, wherein the pad may be an input pad, an output pad, or a V.sub.DD power rail. The circuit includes a thick oxide device, a capacitor, and a resistor. The thick oxide device is configured with its drain and source connected to the pad and circuit ground V.sub.SS, respectively. The gate of the thick oxide device is tied to the pad, and the oxide device bulk is coupled by the resistor to circuit ground V.sub.SS. The capacitor is connected between the pad and the bulk of the thick oxide device. The bulk of the device is constructed by a P-well region formed in a substrate. The capacitor is formed between the pad and a polysilicon layer just therebelow, without consuming extra layout areas. When a positive-to-ground ESD pulse is conducted at the pad, the capacitor will couple the ESD voltage to the well region, forward bias the bulk/source junction, and then turn on the thick oxide device operated in a bipolar mode to bypass the ESD stress. Moreover, a diode is connected between the pad and circuit ground by its cathode and anode, respectively, to bypass a negative-to-ground ESD pulse. The diode can be an extra or built-in PN junction.