The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 1999

Filed:

May. 02, 1996
Applicant:
Inventors:

Mario A Bolanos, Plano, TX (US);

Jeremias L Libres, Dallas, TX (US);

Tay Liang Chee, Singapore, SG;

Ireneus J Pas, Rozendaal, NL;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
B29C / ; B29C / ;
U.S. Cl.
CPC ...
2643285 ; 2643284 ; 26427217 ;
Abstract

A method and apparatus for providing a prepackaged mold compound for use in encapsulating integrated circuit die and leadframe assemblies. A piece of mold compound 71 is placed in a receptacle 91 in a bottom mold chase 83. The receptacle 91 is coupled to a group of die cavities 85 by runners 87. Leadframe strip assemblies containing leadframes, integrated circuit dies, and bond wires coupling the leadframes and dies are placed over the bottom mold chase 83 such that the integrated circuit dies are each centered over a bottom mold die cavity 85. A top mold chase 93 is placed over the bottom mold chase and the prepackaged mold compound 71. The prepackaged mold compound 71 is a piece of mold compound 73 packaged in a plastic film which has sealed edges 77. The edges are peelable seals, which are released during the molding process. The mold compound 73 is then forced through the seals during the molding process by the pressure applied by a plunger 101. The plunger 101 can be applied using variable speed and pressure to control the rate the mold compound 73 fills the cavities in the top and bottom mold chases, thereby avoiding voids in the completed packages and minimizing wire sweep of the bond wires of the integrated circuit assemblies.


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