The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 1999
Filed:
Mar. 30, 1998
Jack Eng, Bellmore, NY (US);
Joseph Y Chan, Kings Park, NY (US);
Willem G Einthoven, Somerset, NJ (US);
John E Amato, Taipei, TW;
Sandy Tan, Farmingdale, NY (US);
Lawrence LaTerza, Miller Pl., NY (US);
Gregory Zakaluk, Seaford, NY (US);
Dennis Garbis, South Huntington, NY (US);
General Semiconductor, Inc., Melville, NY (US);
Abstract
Starting with a semiconductor wafer of known type including an internal, planar p-n junction parallel to major surfaces of the wafer, one of the wafer surfaces is covered with a masking layer of silicon nitride. A plurality of intersecting grooves are then sawed through the masking layer for forming a plurality of mesas having sloped walls with each mesa including a portion of the planar p-n junction having edges which intersect and are exposed by the mesa walls. The groove walls and exposed junction edges are glass encapsulated in a process including heating the wafer. The masking layers are then removed in a selective etching process not requiring a patterned etchant mask, and the now exposed silicon surfaces at the top of the mesas, as well as the opposite surface of the wafer, are metal plated. The wafer is then diced along planes through the grooves for providing individual chips each having a glass passivated mesa thereon.