The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 1999

Filed:

May. 07, 1997
Applicant:
Inventors:

Kishor V Desai, Vestal, NY (US);

Joseph Hromek, Endwell, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R / ; H01R / ; H01R / ; H05K / ;
U.S. Cl.
CPC ...
324757 ; 324755 ; 174261 ; 439 66 ;
Abstract

Temporary connections are formed to a flip-chip style chip having solder bumps or preforms protruding therefrom for testing and burn-in while avoiding distortion of the solder bumps or preforms and avoiding wear and damage to a test or burn-in jig such as a ball grid array by the use of a preferably resilient bucketed interposer which includes recesses which have a depth greater than the protrusion of the solder bumps or preforms and, preferably are narrowed at one side to a tear-drop shape. Metallization in the recesses and contacts on the interposer which mate with the test or burn-in jig are preferably textured with dendrites to be self-cleaning. A bevelled tongue and groove arrangement translates a slight compressive force to a slight shearing force between the interposer and the chip to ensure good connections to the protruding solder bumps or preforms on the chip. Any deformation of the solder bumps or preforms thus tends to only improve accuracy of positioning of the solder bumps or preforms and avoids solder voiding due to compression distortion of the solder bumps or preforms. Full burn-in and functional testing can then identify 'known good' chips or dies before package completion, particularly to avoid rework of modular circuit packages.


Find Patent Forward Citations

Loading…