Frequency trimmable oscillator and frequency multiplier

Abstract

A pure MOS-implementable oscillator requires no trimming to make the oscillation frequency Vdd independent, but permits trimming to compensate for process and fabrication variations. A current generator creates a core reference current Iosc0, mirrored programmable trim currents, and dynamic reference voltages that do not require a constant Vdd source. A programmable delay unit provides value-programmable capacitors that receive mirrored currents A.times.(M/N).times.Iosc0, where A is a MOS channel W/L ratio constant, and M and N are integers. The currents create ramp-like voltage signals across the capacitors, the slewrate being A.times.(M/N).times.Iosc0/capacitance. A comparator unit compares the ramp-like signals, which ramp-down from Vdd, against a (Vdd-Vt) reference voltage (Vt being a MOS threshold voltage). The comparator unit outputs complementary signals that toggle a set-reset flipflop, whose output is the oscillator output signal. This signal is fedback to the programmable delay unit to toggle on and off the current flow that determines oscillation period. Frequency change due to discrepancies between anticipated and realized load resistors and capacitors may be coarse and/or fine trimmed, for example by incrementally varying M and/or by turning-on a current-providing MOS device having an appropriate W/L value for A. The oscillator includes two programmable delay paths and can accept an input oscillator signal and output a signal whose frequency is a non-integer or integer multiple, simply by varying capacitor ratios.