The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 1999

Filed:

Nov. 18, 1996
Applicant:
Inventors:

Dan Maydan, Los Altos Hills, CA (US);

Sasson Somekh, Los Altos Hills, CA (US);

Ashok Sinha, Foster City, CA (US);

Kevin Fairbairn, Saratoga, CA (US);

Christopher Lane, Saratoga, CA (US);

Kelly Colborne, Sunnyvale, CA (US);

Hari K Ponnekanti, Santa Clara, CA (US);

W N(Nick) Taylor, Dublin, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
C23C / ; C23F / ;
U.S. Cl.
CPC ...
118719 ; 156345 ; 20429825 ; 20429835 ;
Abstract

The present invention generally provides a cassette-to-cassette vacuum processing system which concurrently processes multiple wafers and combines the advantages of single wafer process chambers and multiple wafer handling for high quality wafer processing, high wafer throughput and reduced footprint. In accordance with one aspect of the invention, the system is preferably a staged vacuum system which generally includes a loadlock chamber for introducing wafers into the system and which also provides wafer cooling following processing, a transfer chamber for housing a wafer handler, and one or more processing chambers each having two or more processing regions which are isolatable from each other and preferably share a common gas supply and a common exhaust pump. The processing regions also preferably include separate gas distribution assemblies and RF power sources to provide a uniform plasma density over a wafer surface in each processing region. The processing chambers are configured to allow multiple, isolated processes to be performed concurrently in at least two processing regions so that at least two wafers can be processed simultaneously in a chamber with a high degree of process control provided by shared gas sources, shared exhaust systems, separate gas distribution assemblies, separate RF power sources, and separate temperature control systems.

Published as:
EP0843340A2; JPH10154739A; KR19980042482A; US5855681A; EP0843340A3; TW373230B; EP0843340B1; DE69730097D1; DE69730097T2; KR100503125B1; JP2009094530A; JP2013179309A;

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