The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 17, 1998
Filed:
Jun. 13, 1996
Rustom F Irani, Santa Clara, CA (US);
Boaz Eitan, Ra'anana, IL;
Mark Michael Nelson, Pocatello, ID (US);
Larry Willis Petersen, Pocatello, ID (US);
Waferscale Integration Inc., Fremont, CA (US);
American Microsystems, Inc., Pocatello, ID (US);
Abstract
A read only memory (ROM) array is disclosed which includes a) a voltage supply providing an operating voltage level, b) a plurality of word-lines, c) a multiplicity of ROM transistors, and d) a word-line clamper. The ROM transistors are divided into turned on and turned off transistors. Each ROM transistor has a gate connected to one of the word-lines, a gate oxide beneath the gate, whose thickness is less than 250 .ANG., and a channel beneath the gate oxide. The turned off transistors additionally have a ROM implant in their channel whose dosage is no larger than the amount which generates a predetermined desired minimal band-to-band tunneling current The ROM implant and gate oxide thickness define a threshold voltage for the tamed off tranistors, the threshold voltage being less than the operating voltage level. The word-line damper provides a word-line voltage to each of the word-lines, the word-line voltage being clamped to a voltage level no higher than the threshold voltage of the turned off transistor.