The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 1998

Filed:

Jan. 29, 1997
Applicant:
Inventors:

Tetsuya Yamamoto, Mine, JP;

Hideyuki Yoshino, Ube, JP;

Akihiro Hidaka, Yoshiki-gun, JP;

Roy Bell, Gilbert, AZ (US);

Rusli Othman, Kedah, MY;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K / ;
U.S. Cl.
CPC ...
174 521 ; 174 523 ;
Abstract

A lid for sealing a semiconductor package containing a semiconductor chip, a semiconductor package making use of the lid, and a method for producing the lid. The lid has a solder layer along the peripheral side of a ceramic plate. The solder layer has a portion of an increased solder thickness and a portion of a reduced solder thickness extending along the peripheral direction. When sealing the semiconductor package, a gas confined within the inside of the semiconductor chip mounting site of the package substrate may be discharged from the semiconductor package for realizing hermetic sealing.


Find Patent Forward Citations

Yamamoto, Tetsuya. (1998). Lid with variable solder layer for sealing semiconductor package, (U.S. Patent No. 5821455). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5821455

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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