High performance method of and system for selecting one of a plurality

Abstract

A circuit is provided for selecting one of plurality of integrated circuit chips with a minimum number of chip select signal lines. A first embodiment includes a plurality of paired address lines; each line in each pair provides a logical complementary signal. Only a selected one of the lines of each pair is coupled to integrated circuit. Each of the integrated circuits is coupled to a unique combination of these selected lines of the pairs. In a second embodiment a select signal is clocked by a controller from one of the integrated circuits to the next in a fashion similar to a shift register. Once the select signal is present in the desired integrated circuit, the controller then provides an enable signal to all the integrated circuits which enables only that desired integrated circuit. In yet another embodiment, the address lines are also used a chip select signal lines, one address line for each integrated circuit. A Chip.sub.-- select.sub.-- clock.sub.-- enable line is used to toggle the chip select signal to the desired device. In a preferred embodiment, a unique value is stored in a register on each integrated circuit. A controller places the unique value of a desired integrated circuit onto a bus. A comparator in each integrated circuit determines which chip has been selected. The controller then provides a chip select signal to activate the desired integrated circuit.