The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 1998
Filed:
Jun. 09, 1997
Chi-Shen Lo, Hsin-Chu, TW;
Chao-Hsin Chang, Hsin-Chu, TW;
Chia-Hsiang Chen, Hsin-Chu, TW;
Hsien-Wen Chang, Hsin-Chu, TW;
Chih-Heng Shen, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
A simple, non critical, low cost process step is added to the manufacture of integrated circuit wafers to remove a ridge of dielectric material remaining at the flat edge of the wafer after an edge rinse has removed the ridge of dielectric from the circular edges of the wafer. A layer of dielectric, such as Spin-On-Glass or the like, is formed on the wafer. An edge rinse is then used to remove the ridge of dielectric formed at the wafer edge, however the edge rinse does not remove the ridge of dielectric at the flat edge of the wafer. A layer of photoresist is formed on the wafer, selectively exposed, and developed to form a photoresist mask. The flat edge of the wafer is then dipped in buffered oxide etch to remove the dielectric material at the flat edge of the wafer. The photoresist mask is then stripped and processing of the wafer is continued. Damage to dielectric material at the flat edge of the wafer, which can cause particles to flake off and become a source of defects in subsequent process steps, in thereby avoided.