The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 1998
Filed:
Jan. 03, 1996
Koichiro Mashiko, Tokyo, JP;
Kimio Ueda, Tokyo, JP;
Hiroaki Suzuki, Tokyo, JP;
Hiroyuki Morinaka, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A logic circuit (L.sub.i) is connected between a virtual power supply line (VDDV) connected to an actual power supply (VDD) through a PMOS transistor (Q1) and a virtual grounding line (GNDV) connected to an actual ground (GND) through an NMOS transistor (Q2). During an active period, the transistors (Q1, Q2) are constantly conducting, and the virtual power supply line (VDDV) and virtual grounding line (GNDV) are at the power supply potential (VDD) and ground potential (GND), respectively. During a standby period, the transistors (Q1, Q2) periodically repeat conduction/non-conduction to charge and discharge the virtual power supply line (VDDV) and virtual grounding line (GNDV), suppressing power consumption while preventing loss of information held by the logic circuit (L.sub.i).
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile