The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 1998
Filed:
Oct. 11, 1996
Jun-Hee Lim, Seoul, KR;
Mun-Mo Jeong, Seoul, KR;
LG Semicon Co., Ltd., Chungcheongbuk-do, KR;
Abstract
A method of fabricating a capacitor of a semiconductor memory device includes the steps of: forming an interlevel insulating layer on a semiconductor substrate on which the capacitor will be formed, selectively etching a portion of the interlevel insulating layer placed on a capacitor forming portion to form a capacitor node hole, and forming a first temporary layer on the interlevel insulating layer, including a portion of the interlevel insulating layer in which the capacitor node hole is formed; forming a contact hole beneath the capacitor node hole in a capacitor contact portion; forming a conductive layer on the first temporary layer to bury the contact hole and the capacitor node hole, and then forming a second temporary layer on the conductive layer; etching back the second temporary layer through anisotropic etching process to expose the conductive layer, and to simultaneously form a temporary pillar layer inside the capacitor node hole, the temporary pillar layer being substantially surrounded by the conductive layer; removing a portion of the conductive layer placed on a portion other than the capacitor forming portion, to form a first capacitor electrode and to expose at least a portion of the first temporary layer; and removing remaining portions of the first and second temporary layers to expose an upper portion of the first capacitor electrode, forming a dielectric layer on a surface of the first capacitor electrode, and forming a second capacitor electrode on a surface of the dielectric layer.