Method for eliminating multiple output switching timing skews in a

Abstract

A source synchronous computer system to ensure the capturing of signals transmitted from a first component to a second component. An integrated circuit operating on a core clock signal and an I/O clock signal, the circuit comprising a plurality of data drivers and a plurality of delayed I/O clock generators, wherein the I/O clock generators generate delayed I/O clocks signals that follow the I/O clock signal by a phase multiple of the core clock signal. The integrated circuit outputs data through output nodes that are synchronized with I/O clock signal. By outputting data signals in the I/O clock domain and using the delayed I/O clock signals to synchronize transmission with external components, the integrated circuit ensures that the data signals are valid before the external component latches the data. A set of data signals and a delayed I/O clock are generated from similar drivers to further ensure that the data signal is valid before the external component latches the data.