The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 1998
Filed:
Apr. 24, 1996
Minoru Kobayashi, Saitama, JP;
Shinichiro Kuroe, Saitama, JP;
Advantest Corp., Tokyo, JP;
Abstract
A delay time stabilization circuit is used in a timing generator which provides a reference timing of a semiconductor IC test system. The delay time stabilization circuit includes a delay control circuit, a period generator which generates period signals necessary for DUT (device under test) testing, a loop forming switch, and a period counter 31 for counting the period in a loop circuit. The calibration process starts by setting the loop forming switch. A start pulse generation circuit generates n pulses when receiving one trigger pulse which pass through a CMOS variable delay circuit and the loop circuit to a 1/n divider circuit. The n pulses are divided by n to produce a signal pulse which triggers the start pulse generation circuit. In the DUT testing, the period generator 11 generates the period signal necessary for the testing which is the same repetition rate as generated by the start pulse generation circuit, resulting in the same power dissipation in the calibration process and the DUT testing.