The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 1998

Filed:

Dec. 23, 1996
Applicant:
Inventors:

Rick Lee Mangold, Lake Worth, FL (US);

James George Lance, Jr, Lake Worth, FL (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438613 ; 438614 ;
Abstract

A process for fabricating a solder bump having an improved geometry includes the steps of evaporatively depositing a first metallization system to form a post having a predetermined volume onto an integrated circuit having a passivation layer defining a die pad window, wherein the length of the post is greater than the width of the post, and wherein the length of the post extends beyond the die pad window over the passivation layer, and evaporatively depositing a second metallization system onto the post to form a cap also having a volume, wherein the first metallization system forming the post and the second metallization system forming the cap, when reflowed, form a eutectic solder bump.


Find Patent Forward Citations

Mangold, Rick. (1998). Process for fabricating a solder bump for a flip chip integrated circuit (U.S. Patent No. 5759910). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5759910

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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