The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 1998

Filed:

Nov. 14, 1996
Applicant:
Inventors:

Peter W Lee, Saratoga, CA (US);

Hsing-Ya Tsao, Hsin-Chu, TW;

Fu-Chang Hsu, Hsin-Chu, TW;

Assignee:

Aplus Integrated Circuits, Inc., Saratoga, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11L / ;
U.S. Cl.
CPC ...
36518506 ; 36518513 ;
Abstract

A memory cell array of a flash electrically erasable programmable read only memory (EEPROM) includes a plurality of transistor cells arranged in rows and columns. The sources of transistor cells in the same memory block are connected to a main source line through a control gate, as are the drains. The separate source and drains in the column direction are designed for a bit-based write capability. Writing, such as erasing or programming, of a selected transistor cell uses the Fowler-Nordheim tunneling method and can be accomplished due to the programming or erase inhibit voltage that is applied to non-selected transistor cells. The associated circuitry for bit-based writing, as well as methods of programming and erasing the memory cell array, with over-program and over-erase repair capability, are also disclosed.


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