The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 1998

Filed:

Sep. 06, 1996
Applicant:
Inventors:

Hiroyuki Morinaka, Tokyo, JP;

Kimio Ueda, Tokyo, JP;

Koichiro Mashiko, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257315 ; 257318 ; 257321 ;
Abstract

A semiconductor integrated circuit device having a SOI structure which can prevent a deterioration in the breakdown voltage of a transistor without damaging integration, and a method for manufacturing the semiconductor integrated circuit device are obtained. An embedded oxide film is not formed over the whole face of a P type silicon layer but has an opening in a region which is placed below a gate electrode. The opening is filled in to form a penetration P layer. Accordingly, a SOI layer is electrically connected to the P type silicon layer through the penetration P layer. The plane position and shape of the gate electrode conform to those of the penetration P layer.


Find Patent Forward Citations

Morinaka, Hiroyuki. (1998). Semiconductor integrated circuit device, method for manufacturing the (U.S. Patent No. 5747847). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5747847

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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