The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 1998
Filed:
Aug. 30, 1996
Masanori Numano, Kanagawa-ken, JP;
Norihiko Tsuchiya, Tokyo, JP;
Hiroyasu Kubota, Chiba-ken, JP;
Yoshiaki Matsushita, Kanagawa-ken, JP;
Yoshiki Hayashi, Kanagawa-ken, JP;
Yukihiro Ushiku, Kanagawa-ken, JP;
Atsushi Yagishita, Kanagawa-ken, JP;
Satoshi Inaba, Tokyo, JP;
Yasunori Okayama, Kanagawa-ken, JP;
Minoru Takahashi, Kanagawa-ken, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
Element isolation technique for LSIs having a fine pattern of sub-micron class or finer. A high strained region doped with impurities at a high concentration is formed under, and remote from, a buried insulating material (dielectrics) layer for element isolation. With this buried dielectrics element isolation (BDEI) structure, since the high strained layer exists just under the buried dielectrics layer, crystal defects generated near the buried dielectrics layer due to strain caused by a difference of thermal expansion coefficient between a semiconductor layer and the buried dielectrics layer, are moved toward the high strained layer. Accordingly, the crystal defects do not reach an active region where active elements are formed, so that leakage current in the p-n junction formed in the active layer can be advantageously reduced.