The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 1998
Filed:
Jun. 18, 1997
Julie Huang, Chinchu, TW;
Eric Wang, Chinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
An improved process for fabricating cylindrical capacitors for use in DRAMs is described wherein the silicon nitride etch stop layer is eliminated. The etch stop layer is normally used to halt etching during the formation of the dielectric cylinder that is used as a substrate on which the cylindrical electrode gets built. If etching is allowed to proceed, the underlying dielectric layer on which the cylinder rests will also be removed. In place of the etch stop layer, the present invention calls for two dielectric layers that have generally similar properties in other respects but substantially different etch rates. For the fast etching dielectric, O.sub.3 TEOS is used while, for the slow etching dielectric, BPTEOS is used. When etched in 10:1 BOE a differential etch rate of about 10 times is obtained so that formation of a O.sub.3 TEOS cylindrical substrate can be completed without significantly eroding the underlying BPTEOS support layer.