The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 1998

Filed:

Nov. 14, 1995
Applicant:
Inventors:

Krishna K Parat, Palo Alto, CA (US);

Glen N Wada, Fremont, CA (US);

Gregory E Atwood, San Jose, CA (US);

Daniel N Tang, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438586 ; 438593 ; 438595 ; 438637 ; 438211 ;
Abstract

The encapsulation of gate stacks of a semiconductor device in an oxide insulative layer and in a silicon nitride etch-stop layer allows the formation of a contact filling for connection to underlying diffusion regions without risk of accidental diffusion contact to gate shorts created by the contact filling. As a result, the gate stacks may be patterned closer together, thus reducing the cell size and increasing the cell density. Furthermore, use of the etch-stop layer makes contact lithography easier since the size of the contact opening can be increased and contact alignment tolerance made less stringent without concern of increasing the cell size or of creating diffusion contact to gate shorts.


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