The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 1998
Filed:
Jun. 02, 1995
Shuji Ikeda, Koganei, JP;
Satoshi Meguro, Hinode-machi, JP;
Soichiro Hashiba, Hamura-machi, JP;
Isamu Kuramoto, Higashiyamato, JP;
Atsuyoshi Koike, Kokubunji, JP;
Katsuro Sasaki, Fuchuu, JP;
Koichiro Ishibashi, Tokyo, JP;
Toshiaki Yamanaka, Iruma, JP;
Naotaka Hashimoto, Hachioji, JP;
Nobuyuki Moriwaki, Kyoto, JP;
Shigeru Takahashi, Hitachiohta, JP;
Atsushi Hiraishi, Ohme, JP;
Yutaka Kobayashi, Katsuta, JP;
Seigou Yukutake, Hitachi, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
Herein disclosed is a semiconductor integrated circuit device comprising an SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs, and a method of forming this device. The gate electrodes of the drive MISFETs and of the transfer MISFETs of the memory cell, and the word lines, are individually formed of different conductive layers. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The source line is formed of a conductive layer identical to that of the word line. An oxidation resisting film is formed on the gate electrodes of the drive MISFETs so as to reduce stress caused by oxidization of edge portions of these gate electrodes, and to reduce a resulting leakage current. A thickness of an oxide film formed on gate electrodes of the transfer MISFETs and word lines is thicker than an oxide film formed on gate electrodes of the drive MISFETs, so that data line pads can be formed in self-alignment with the oxide film and side wall spacers on the gate electrodes of the transfer MISFETs.