Method for eliminating process variation timing skews in a source

Abstract

A source synchronous computer system to ensure the capturing of signals transmitted from a first component to a second component. An integrated circuit operating on a core clock signal and an I/O clock signal, the integrated circuit comprising a plurality of data drivers and a plurality of external I/O clock generators, wherein the external I/O clock generators generate external I/O clocks signals using circuitry identical to the data drivers except for a slight increase in the channel length of the pre-driver and driver transistors. These transistors control the transition time of the external I/O clock output node. By outputting data signals in the I/O clock domain and using the external I/O clock signals to synchronize transmission with external components, the integrated circuit ensures that the data signals transition before the transitions of the external I/O clock signals regardless of process induced signal variations. A set of data signals and a delayed I/O clock are generated from similar drivers to further ensure that the data signals are asserted before the transition of the external I/O clock signal.