Method of approach to improve metal lithography and via-plug integration

Abstract

A method is described wherein topography of semiconductor wafer surfaces is improved. This is accomplished by introducing a specific planarization technique after the deposition of the first level of metal. It is shown further that the technique involves a combination of oxide and spin-on-glass layers. The resulting dielectric system is etched back in such a way that the resulting two-tiered metal-oxide structure and the surface thereover offers a uniformly flat depth-of-field which in turn makes possible the use of submicron optolithographic tools for the ultra high density integrated circuit chips. In an attempt to improve further the required flatness for submicron technologies, it is shown that silicon nitride may be introduced at a judiciously chosen process step so as to minimize the propagation of surface irregularities from one layer to another through minimizing the so-called microloading effect. It is found that the presence of silicon nitride for this purpose also serves the purposes of eliminating, what are called, the 'exploding vias'.