The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 1998

Filed:

Jul. 17, 1996
Applicant:
Inventors:

Chen-Chiu Hsue, Hsin-Chu, TW;

Gary Hong, Hsin-Chu, TW;

Ming-Tzong Yang, Hsin-Chu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438254 ; 438397 ;
Abstract

A method for fabricating a capacitor having a fin-shaped electrode on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a metal-oxide-semiconductor field effect transistor (MOSFET), having one capacitor aligned over and contacting the source/drain of the MOSFET in the device region. The capacitor is increased in capacitance by forming a multilayer insulator structure over the storage capacitor area and recessing alternate layers, then using the form as a mold for forming a polysilicon fin-like bottom capacitor electrode. The remaining multilayer mold is removed and a high dielectric constant insulator is deposited on the bottom electrode as the inter-electrode dielectric. The top capacitor electrode is formed by depositing a doped polysilicon layer which also fills the recesses in the bottom electrode forming inter-digitized fin-shaped top and bottom capacitor electrodes and completing a dynamic random access memory (DRAM) cell.


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