The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 1998
Filed:
Dec. 13, 1995
Kiyoshi Hisatomi, Yokohama, JP;
Yuuichi Mikata, Yokohama, JP;
Sakae Funo, Yokohama, JP;
Katsunori Ishihara, Hiratsuka, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
In a silicon substrate, impurity diffusion layers, serving as source and drain regions, are formed to be separated from each other. A gate insulation film is formed on the silicon substrate between these source and drain regions. The gate insulation film is a silicon oxide film containing Cl having concentration of more than 1.times.10.sup.18 atoms/cm.sup.3 and less than 2.times.10.sup.20 atoms/cm.sup.3, and the gate insulation film is formed on the silicon substrate by low-pressure CVD. A gate electrode, formed of a polysilicon layer, is formed on the gate insulation film. An inter-level insulation film is formed on a resultant structure. A contact hole is formed on each of the source and drain regions of the inter-level insulation film. A drain electrode is formed on the inter-level insulation film, and connected to the drain region through the contact hole. A source electrode is formed on the inter-level insulation film, and connected to the source region through the contact hole.